If you’ve been following the news about 5G, you know that it significantly boosts bandwidth up to 10 Gb/s. It also has sub-1-ms system latency paired with a considerable reduction in power consumption over existing networks. 5G will enable a host of new applications in the Industrial Internet of Things (IIoT), vehicle-to-vehicle communication, and connected edge computing.
In addition to high bandwidth and ultra-low latency, these applications require two other properties that don’t get much attention: 99.99x% reliability and 24×7 availability. This article discusses important selection criterion for NOR flash memories in wireless-infrastructure applications.
The need to respond to changing market standards in a compressed time-to-market window has led to the widespread use of field-programmable gate arrays (FPGAs) as well as complementary system-on-chip devices (SoCs) in a broad range of wireless infrastructure applications. FPGAs and SoCs require configuration each time the system is powered up. The FPGA and SoC can be configured by diverse types of memories such as Flash, eMMC, unmanaged NAND, and SD cards.
Unlike NAND flash (managed or unmanaged) and SD cards, NOR flash memories provide high reliability with low latency in initial response and boot. In addition, advances such as MirrorBit technology, which stores two bits per memory cell, supports greater density scaling compared to floating-gate technology. Greater density enables monolithic 1-Gb and higher density NOR flash products required for 5G wireless infrastructure. Due to these characteristics, NOR flash memories have found widespread use in wireless-infrastructure applications to configure FPGAs and SoCs to quickly and reliably boot these devices.
5G can use bands below 6 GHz and those at 28 GHz. These carrier frequencies are far higher than typical 4G LTE frequencies. While the higher carrier frequency has the potential to support many more channels as frequency increases, propagation worsens. At these frequencies, connections are limited to a short-range line-of-sight due to free-air attenuation and the signal’s inability to penetrate solids.
Accordingly, transceivers will have to rely on techniques such as beamforming. Beamforming provides constructive interference to boost the signal at receiving ends, but cells must be located closer together.
MIMO antennas and their RF front ends are key to implementing 5G access units (see figure). For base stations, the antennas will probably be 64×64 arrays. A 64×64 MIMO will explode fronthaul (the connection between the antenna and the digital front end) bandwidth requirements. The FPGA/SoC used in the access unit will require significantly more logic elements (higher density), greater DSP capability, and transceivers compared to those used in 4G LTE digital units.
In this 5G system, a 64×64 antenna array increases the data transfer between the antenna and the digital front end, leading to higher processing requirements in the Access Unit (AU) and Cloud Unit (CU).
These increased requirements will lead to larger configuration images needing higher-density monolithic NOR flash memories used to configure the FPGA/SoC. Such densities will range between 512 Mb to 2 Gb for 5G access units.
FPGAs and SoCs can configure/boot from flash memories with two distinct interface types: parallel and serial. While a parallel interface allows for faster read-write times, too many IOs are required for interfacing. For example, consider interfacing a 1-Gb parallel NOR flash with a FPGA. The number of IOs required would be 49. But with every subsequent increase in density (2G, 4G, 8G etc.), the number of pins increases by 1.
NOR flash serial interfaces are based on the SPI interfaces commonly found on controllers. They come in SPI (1-bit), Dual-SPI (2-bit), Quad-SPI or Q-SPI (4-bit), and even Octal-SPI (8-bit) interfaces.
The current trend is that engineers are migrating from parallel to serial interfaces for new system designs. Serial interfaces reduce pin count for both the memory and the SoC, shrinking the PCB for lower cost and smaller form factors. Octal SPI and HyperBus interfaces now offer performance up to 400 MB/s, rivaling that of parallel interfaces. Note that while FPGAs like the recently announced Xilinx Versal support both Octal SPI and Q-SPI interfaces, 14-nm and higher-geometry FPGAs/SoCs support only Q-SPI interfaces.
In addition to parallel and serial interfaces, voltage requirements for the interface are also an important selection criterion. Today’s FPGAs/SoCs used for 5G will be developed on the most advanced process nodes, where they’re reducing 3-V I/O support to enhance IC reliability and performance. Most flash memories on the market are 3-V components (meaning they require operating voltage in the range of 2.7 to 3.6 V), whereas 1.8-V NOR flash components (these components need operating voltage between 1.7 and 2.0 V) are required for the latest FPGAs/SoCs.
As FPGAs and other controllers continue their march to lower geometries and supply voltages, 1.2-V NOR flash components have become available. While most NOR flash components require only a single supply voltage, the 1.2-V components require two different supplies—one for the core and the other for the IOs (the high and low conditions for inputs and outputs are defined in reference to the VIO). Separating VIO from VCC provides greater flexibility to system designers at the expense of an additional power supply.
Almost all 1.2-V NOR flash memories on the market are targeted to consumer applications. Consumer applications are inherently low density compared to the needs of 5G wireless infrastructure applications, making them unsuitable for configuring FPGAs in these applications. Thus, 1.8-V NOR flash memories remain the most suitable NOR flash for configuring a broad range of FPGAs or booting SoCs for wireless infrastructure applications, due to available density options and broad support for 1.8V IO in FPGAs.
Temperature Rating and Low-Power Modes
Wireless-infrastructure equipment, especially digital front ends such as the radio and small cells, are often installed outside and face extreme environmental conditions. To make matters worse, system designers may be limited in ability to install heat sinks and fans on components used in 5G. Accordingly, designers typically select NOR flash components in the industrial-plus temperature grade (−40 to +105°C) to withstand the harsh environmental conditions and provide an additional guard band in power consumption. They’re also preferred because they help ensure boot-up and operation at these high temperatures.
Deep-Power-Down and Standby Modes
The NOR flash component is typically idle in between FPGA/SoC configuration cycles. Deep-power-down and standby modes found on some NOR flash components can help reduce power consumption by putting the NOR flash component in a low-power state after configuration is completed.
Endurance and Data Retention
NOR flash has been optimized for reliability and performance as opposed to cost (unlike consumer-oriented technologies such as NAND flash and SD cards). This technology uses a relatively larger memory cell that provides high endurance and long data retention. It’s common to find products with 100K program/erase (P/E) cycles endurance and up to 10 years data retention.
Note that generally one would expect to not worry about endurance for such applications, as the flash may only be written to a small number of times. This is true if we only consider storing the configuration image in the flash. Some designers also use flash to cache transactional data and system error logs. Under this usage scenario, system logs are updated in flash every few minutes. As a result, the total number of P/E cycles over an 8- to 10-year lifespan can exceed the max endurance spec without wear leveling.
Newer products on the market offer engineers the ability to optimize the balance between endurance and data retention by offering the choice of up to 1M P/E cycle endurance or 25-year data retention. These higher-reliability products sometimes come with detailed failure-mode effects analysis, which can help designers design systems to meet or beat the ultra-high reliability and availability requirements of the 5G spec. For example, Cypress provides several functional safety documents, including device safety manual and detailed safety analysis reports, which document product safety architecture and assumed usage, summary FIT rates, FMEDA results, full safety analysis down to block level, safety mechanisms and diagnostics coverage (see NOR Flash for Automotive and Functional Safety).
Recently, there was a news report of long term, large-scale attacks targeting telecom companies around the world. According to the security research firm Cybereason, the attackers exfiltrated Call Data Records in this attack, but they had gained control of the networks and could have even shut them down.
Due to such incidents, there’s growing in interest in securing wireless-infrastructure equipment. The simplest way to add security to these systems is to secure the configuration image/boot code through deployment of secure boot and access control processes. In response to growing interest in securing embedded systems, NOR flash vendors have started developing products with built-in security features, such as public-key-infrastructure-based authentication and access control, and secure boot. These features can add additional measures to ensure security of proprietary IP, prevent tampering of configuration image/boot code, and make certain that the network remains continuously available.
NOR flash is favored over NAND and SD cards for storing FPGA configuration images and SoC boot code. 5G wireless infrastructure applications need 1 Gb or higher density, 1.8 V Q-SPI or Octal SPI, industrial-plus temperature grade NOR flash to configure or boot the FPGA and/or SoC used in the system.
As designers begin work on 5G wireless-infrastructure products, there’s an increased focus on fail-safe operation to meet the requirements of applications such as eHealth, IIoT, and self-driving cars. Flash-memory vendors are now beginning to introduce products that offer functional safety and secure-boot mechanisms. These features enable designers to offload some of the processing for system-level safety and security functions to the memory. In addition, the available collateral helps aid implementation of these functions and reduce time to market. Choosing the right memory ultimately helps ensure the success of the product.
Manish Garg works with the Memory Products Division at Cypress Semiconductor in Product Marketing.